DIGITAL LOGIC (conti..)

Rule 1. A + 0 = A


A variable ORed with 0 is always equal to the variable. If the input variable A is 1, the output variable X is 1, which is equal to A. If A is 0, the output is 0, which is also equal to A. This rule is illustrated in Fig.(4-6), where the lower input is fixed at 0.

Fig.(4-6)

Rule 2. A + 1 = 1


A variable ORed with 1 is always equal to 1. A 1 on an input to an OR gate produces a 1 on the output, regardless of the value of the variable on the other input. This rule is illustrated in Fig.(4-7), where the lower input is fixed at 1.

Fig.(4-7)

Rule 3. A . 0 = 0


A variable ANDed with 0 is always equal to 0. Any time one input to an AND gate is 0, the output is 0, regardless of the value of the variable on the other input. This rule is illustrated in Fig.(4-8), where the lower input is fixed at 0.

Fig.(4-8)

Rule 4. A . 1 = A


A variable ANDed with 1 is always equal to the variable. If A is 0 the output of the AND gate is 0. If A is 1, the output of the AND gate is 1 because both inputs are now 1s. This rule is shown in Fig.(4-9), where the lower input is fixed at 1.

Fig.(4-9)

Rule 5. A + A = A


A variable ORed with itself is always equal to the variable. If A is 0, then 0 + 0 = 0; and if A is 1, then 1 + 1 = 1. This is shown in Fig.(4-10), where both inputs are the same variable.

Fig.(4-10)

                                                                       By:Amirul Ramzani

Rule 6. A + A = 1


A variable ORed with its complement is always equal to 1. If A is 0, then 0 +

0 = 0 + 1 = 1. If A is l, then 1 + 1 = 1+ 0 = 1. See Fig.(4-11), where one input is the complement of the other.

Fig.(4-11)

Rule 7. A . A = A


A variable ANDed with itself is always equal to the variable. If A = 0, then 0.0 = 0; and if A = 1. then 1.1 = 1. Fig.(4-12) illustrates this rule.

Fig.(4-12)

Rule 8. A . A = 0

A variable ANDed with its complement is always equal to 0. Either A or A will always be 0: and when a 0 is applied to the input of an AND gate. the output will be 0 also. Fig.(4-13) illustrates this rule.

Fig.(4-13)

Rule 9.  A = A


The double complement of a variable is always equal to the variable. If you start with the variable A and complement (invert) it once, you get A. If you

then take A and complement (invert) it, you get A, which is the original variable. This rule is shown in Fig.(4-14) using inverters.

Fig.(4-14)

Rule 10. A + AB = A


This rule can be proved by applying the distributive law, rule 2, and rule 4 as follows:

A + AB = A( 1 + B) = A . l

= A

Factoring (distributive law) Rule 2: (1 + B) = 1
Rule 4: A . 1 = A

The proof is shown in Table 4-2, which shows the truth table and the resulting logic circuit simplification.

Table 4-2

Rule 11. A + AB = A + B


This rule can be proved as follows:

A + AB = (A + AB) + AB
= (AA + AB) + AB =AA +AB +AA +AB

= (A + A)(A + B) = 1. (A + B)

= A + B


The proof is shown in Table 4-3, which shows the truth table and the resulting logic circuit simplification.

Table 4-3

Rule 10: A = A + AB Rule 7: A = AA

Rule 8: adding AA = 0 Factoring
Rule 6: A + A = 1

Rule 4: drop the 1

Rule 12. (A + B)(A + C) = A + BC

This rule can be proved as follows:

(A + B)(A + C) = AA + AC + AB + BC = A + AC + AB + BC

= A( 1 + C) + AB + BC = A. 1 + AB + BC
= A(1 + B) + BC
= A. 1 + BC

= A + BC

Distributive law
Rule 7: AA = A
Rule 2: 1 + C = 1 Factoring (distributive law) Rule 2: 1 + B = 1

Rule 4: A . 1 = A

The proof is shown in Table 4-4, which shows the truth table and the resulting logic circuit
simplification.

Table 4-4

                                                                                                 


DeMorgan’s Theorems

n DeMorgan’s theorems provide mathematical verification of:

  n the equivalency of the NAND and negative-OR gates

 n the equivalency of the NOR and negative-AND gates.

 n    The complement of two or more ANDed variables is equivalent to the OR of the complements of the individual variables.

 n    The complement of two or more ORed variables is equivalent to the AND of the complements of the individual variables. 

   KARNAUGHT MAP

    INTRODUCTION

•         Applying Boolean algebra can be awkward in order to simplify expressions

•         It is laborious and requires remembering all the laws

•         The Karnaugh map provides a simple and straight-forward method of minimizing Boolean expressions

•    With the Karnaugh map Boolean expressions having up to four and even six variables can be simplified.

•         Karnaugh map provides a pictorial method of grouping together expressions with common factors and therefore eliminating unwanted variables.

•         Karnaugh map can also be described as a truth table.                   

    DEFINITION IN KARNAUGHT MAP

•         Minterm: (Standard product or canonic product term) such as AB’CD or

     A’BCD’ etc. where each variable used once and once only.

•         Maxterm: (Standard sum or canonical sum term) such as (A+B’+C+D) or 

    (A’+B+C+D’) where each variable used once and once only

RULE OF GROUPING 1’S IN KARNAUGHT MAP

    

   1) The group can only contains 1s

   2) Only 1s adjacent cells can be grouped, 

    diagonal grouping is not allowed.

3)  The number of 1s in a group must be power of 2,means a group can contain 

2,4,8 or 16 of 1s

4)      The group must be as large as possible while still following all rules.

5)      All 1s must belong to a group, even if it is a group of one.

6)      Overlapping groups are allowed.

7)      Use the fewest number of groups possible.

Lets watch video one for more detail example and information :

THE UNIVERSAL PROPERTY OF NAND AND NOR GATES

1- The NAND Gate as a Universal Logic Element

The NAND gate is a universal gate because it can be used to produce the NOT, the AND, the OR, and the NOR functions. An inverter can be made from a NAND gate by connecting all of the inputs together and creating, in effect, a single input, as shown in Fig.(6-8)(a) for a 2-input gate. An AND function can be generated by the use of NAND gates alone, as shown in Fig.(6-8)(b). An OR function can be produced with only NAND gates, as illustrated in part (c). Finally. a NOR function is produced as shown in part (d).

Fig.(6-9)

 2- The NOR Gate as a Universal Logic Element

Like the NAND gate, the NOR gate can be used to produce the NOT, AND. OR and NAND functions. A NOT circuit, or inverter, can be made from a NOR gate by connecting all of the inputs together to effectively create a single input, as shown in Fig.(6-10)(a) with a 2-input example. Also, an OR gate can be produced from NOR gates, as illustrated in Fig.(6-10)(b). An AND gate can be constructed by the use of NOR gates, as shown in Fig.(6-10)(c). In this case the NOR gates G 1 and G 2 are used as inverters, and the final output is derived by the use of DeMorgan's theorem as follows:

X=A+B=AB
Fig.(6-10)(d) shows how NOR gates are used t0 form a NAND function.

Fig.(6-10)

                                                                 By:Eisy Humaira